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Short-term Visiting Faculty


Mukherjee Shubu
Distinguished Engineer
12-30 July 2010

Διάφορες Πληροφορίες

Cavium Networks, Marlborough, MA, USA
Dr. Mukherjee is widely recognized as one of the experts on architecture design for soft errors. He has made pioneering contributions towards the design of Redundant Multithreading (RMT) techniques, architectural vulnerability modeling for soft errors, creation of performance modeling infrastructure called Asim (jointly with Dr. Joel Emer), design of the Alpha 21364 interconnection network, and the creation of the first shared memory prediction scheme. In 2009, Shubu won the Maurice-Wilkes award for outstanding contributions to computer architecture. This is the highest award given to a mid-career architect. Prior winners include Dirk Meyer (CEO AMD), Bill Dally (Chief Scientist Nvidia), Steve Scott (CTO Cray), and Anant Agarwal (Prof MIT and Founder of Several Companies). Shubu is also a Fellow of IEEE and Distinguished Member of ACM. He was the General Chair of 2004 ASPLOS and will be the Program Chair for 2011 HPCA conferences. He wrote the seminal book on "Architecture Design for Soft Errors," which has been highly acclaimed by Microprocessor Report as well as researchers and practitioners. Shubu holds 25 patents and has 23 patents pending. He has written over 50 technical papers in top architecture conferences and journals. Currently, Dr Mukherjee is a Distinguished Engineer at Cavium Networks involved in architecting Cavium's next network processor. He is also Adjunct Faculty with the Indian Institute of Technology, Kanpur. In the past, Shubu Mukherjee was a Principal Engineer and Director of Intel's SPEARS Group (Simulation and Pathfinding of Efficient and Reliable Systems). The SPEARS Group was responsible for spearheading architectural change and innovation in the delivery of enterprise processors and chipsets by building and supporting simulation and analytical models of performance, power, and reliability. Shubu has taken 5 innovations in large-scale system monitoring, soft error tolerant micro-architectures, performance simulation, parallel simulation, and on-chip interconnect design from conception to implementation. These innovations have resulted in 100s of millions of dollars in increased revenue for Intel and Compaq, reduced internal costs by 10s of millions of dollars, influenced over a dozen products, and improved customer goodwill significantly.